(1) Field of the Invention
The present invention relates generally to a method of manufacturing an oxide layer, and more particularly, to a method of forming a tunnel oxide layer of a non-volatile memory cell.
(2) Description of the Related Art
Integrated circuits (ICs), such as ultra-large scale integrated (ULSI) circuits, can include as many as one billion transistors or more. The ULSI circuits are generally composed of complementary metal oxide semiconductor field effect transistors (MOSFETs). For a typical random access memory (RAM), the data stored in the memory is volatile. For this reason, a power supply is needed to refresh the data stored in the memory.
On the other hand, non-volatile memories such as Read-only-memories (ROMs), electrically erasable programmable ROM (EEPEOM) or flash memories, are memories into which information is permanently stored.
In order to fabricate a low power non-volatile memory with textured tunnel oxide with high electron injection efficiency and a large charge-to-breakdown, a method for forming high-density non-volatile memories with high capacitive-coupling radio was disclosed in U.S. Pat. No. 6,043,124. According to this prior art, referring first to FIG. 1A, a silicon oxide layer 4 and a thick silicon nitride layer 6 are deposited on a substrate 2. The field oxide (FOX) pattern is now defined by using a conventional photolithography process, and then a dry etching process is performed to etch the thick silicon nitride layer 6 and the pad oxide layer 4. After striping the photoresist, a thermal oxidation process is performed, and the thick field oxide regions 8 are grown to a thickness between 3000 to 8000 angstroms. Thereafter, the silicon nitride layer 6 is optionally removed, and a new silicon nitride layer 10 is created over the substrate 2. After that, another photolithography process is performed to define the tunnel oxide region. An etching process is performed to selectively etch the silicon nitride layer 10 but not the pad oxide layer 4 and expose a portion of the pad oxide layer 4. A thermal oxidation process is then performed to grow a thick thermal oxide 12 on the non-tunnel region, as shown in FIG. 1A.
Referring now to FIG. 1B, the masking silicon nitride film 10 is removed by a wet etching with hot phosphoric acid. An ion implantation process is performed to implant appropriate impurity ions through the silicon oxide layer 4, but not the thick oxide 12, into the substrate 2 to form the source and drain 14. The substrate 2 is then thermal annealed to recover the implantation damage by a preferable method as rapid thermal processing (RTP) process. The dopants are activated and driven in to form the best distribution profile at this step, as shown in FIG. 1B. Thereafter, the silicon oxide 4 is removed by performing a wet etching process. Next, an ultra-thin undoped amorphous silicon (a-Si) film 16 is deposited on the substrate 2. A thermal process is performed to crystallize the a-Si film 16 into polysilicon.
Referring now to FIG. 1C, a thermal oxidation process is performed to form a textured tunnel oxide. Next, a conductive layer 20 is deposited on the substrate 2. A traditional photolithography process is performed to define the floating gate pattern. An anisotropic etching is then performed to etch the conductive layer, so that the floating gate 20 is formed on the active region and a portion of the field oxide region. An ultra-thin interpoly dielectric (IPD) layer 22 is deposited on the surface of the floating gate 20. Finally, another conductive layer is formed on the interpoly dielectric layer 22 to serve as the control gate 24.
The disadvantage of the prior art is that the a-Si film 16 or the HSG layer used in the prior art is not conformal. As a result, the subsequent textured tunnel oxide is not conformal and not uniform in thickness. For this reason, the electron-injection efficiency and charge-to-breakdown of the tunnel oxide layer according to the prior art are not stable and not reliable.
Accordingly, it is a primary object of the present invention to a method of forming a tunnel oxide layer of a non-volatile memory cell.
It is another object of the present invention to provide a non-volatile memory cell with a conformal tunnel oxide layer.
A method of forming a tunnel oxide layer of a non-volatile memory cell is disclosed. First, a first dielectric layer and a second dielectric layer are formed on a semiconductor substrate. After patterning the second dielectric layer to form an opening, the semiconductor substrate is oxidized to form a non-tunnel oxide within the opening. After removing the second dielectric layer, source/drain regions are formed by performing an ion implantation process and an annealing process. After removing the first dielectric layer, an HSG layer with a plurality of HSG grains are formed on the source/drain regions. After that, the HSG layer is partially etched by HF vapor to enlarge a spacing between the HSG grains. In addition to HF vapor, a plasma etching process by fluorine-based gas plasma such as SF6, CF4, and NF3 can achieve the same purpose.
Next, the HSG layer is oxidized to form the tunnel oxide layer. A floating gate of the non-volatile memory cell is formed on the tunnel oxide layer. After forming an interpoly dielectric of the non-volatile memory cell on the floating gate, a control gate of the non-volatile memory cell is deposited on the interpoly dielectric.
The key feature of the present invention is that the tunnel oxide layer is conformal and having uniform thickness. For this reason, the electron-injection efficiency and charge-to-breakdown of the tunnel oxide layer are more stable and can be well-controlled. The non-volatile memory cell according to the present invention is more reliable by means of the conformal tunnel oxide layer.